The present invention relates to a timing generating device which is employed, for example, in IC test equipment, for generating timing signals of various preset periods and phases.
This kind of timing generating device heretofore employed has such an arrangement as shown in FIG. 1. Based on period data set in a period generating section 11 a period generator 12 yields pulses A.sub.1 of a period m (where m is a variable positive integer) times the period T of a reference clock (CK in FIG. 2) which is applied to a terminal 13 and pulses A.sub.2 of a period p (where p is a positive integer smaller than the abovesaid m) times the period T. In FIG. 2 the period mT of the pulses A.sub.1 assumes 8T and 9T alternately and the period pT of the pulses A.sub.2 is 2T within each sequence. The average period of the pulses A.sub.1 is equal to a set period. The period generator 12 further creates fractional period data RD indicative of a delay time shorter than the period T in accordance with low order data of a weight less than the period T in the abovementioned preset period data and the state of generation of the pulses A.sub.1. The fractional period data RD represents the phase difference between the pulses of the preset period and the pulses A.sub.1 upon each occurrence of them.
The pulses A.sub.1 and A.sub.2 and the fractional period data RD are introduced into a fine delay circuit 14, wherein some of the pulses A.sub.1 and A.sub.2 are delayed for a period of time shorter than the period T in accordance with the fractional period data RD and from which they are output as pulses B.sub.1 and B.sub.2, respectively. In the example depicted in FIG. 2 the pulses A.sub.1 are alternately delayed by T/2 and all the pulses A.sub.2 which occur between the pulse A.sub.1 to be delayed and the immediately following pulse A.sub.1 are also delayed by T/2. The period of the pulses B.sub.1 becomes the preset period, i.e. 8.5 T in this example.
The pulses B.sub.1 and B.sub.2 are provided to a coarse delay circuit 16 of a delay generating section 15. The coarse delay circuit 16 is supplied with high order delay data CDH contained in delay data CD set in a delay setting means 17. The coarse delay circuit 16 delays the pulses B.sub.1 in units of the period of the pulses B.sub.2 in accordance with the data CDH, yielding pulses E. FIG. 2 shows the case where the pulses E are each delayed by 4T. The pulses E are applied to a fine delay circuit 18, wherein they are delayed corresponding to low order delay data CDL contained in the delay data CD set in the delay setting means 17, producing pulses F, that is, timing pulses.
Conventionally, the period generator 12 has such an arrangement as depicted in FIG. 3. A period (m+k)T (where m is a positive integer and 0.ltoreq.k&lt;1) to be generated is set in a period setting means 21, from which corresponding period data is provided. Let the number of bits weighted more heavily than a unit period T in the period data and the number of bits weighted less heavily than the unit period T be represented by n.sub.1 and n.sub.2, respectively. In FIG. 3 the bit numbers are n.sub.1 =5 and n.sub.2 =2 and weights of the respective bits are represented by multiples of T. In this example data indicating a value obtained by subtracting T from the period (m+k)T to be generated is provided from the period setting means 21. In the example depicted in FIG. 2 the period (m+k)T to be generated is 8.5 T and period data 0011110 is output correspondingly, as shown in FIG. 3.
A set-reset flip-flop 22 for starting-state setting use and an n.sub.2 -bit D flip-flop 23 for accumulation use are pre-reset by an initialization signal INIT from a terminal 24. As depicted in FIG. 4, upon application of a start signal START to a terminal 25, the flip-flop 22 is set to make its Q output G1 high-level, enabling gates 26 and 27. The start signal START is applied as well to an OR gate 28, the output S.sub.6 of which is provided to a gate 29 to enable it. The reference clock pulses CK from a clock generator 10 are applied via the terminal 13 to the gate 29, from which one of the reference clock pulses is output as the pulse A.sub.1. Further, the output S.sub.6 of the OR gate 28 is provided to a load terminal LO of an n.sub.1 -bit down counter 31. The counter 31 is a clock-synchronous-type counter, in which data of the high order n.sub.1 bits in the output of the period setting means 21, that is, data corresponding to mT, are preset by the negative-going edge of the reference clock CK when the signal S.sub.6 is being applied. That is, the counter 31 is initialized and its count value D.sub.1 is set to 7 in this example, as depicted in FIG. 4. Thereafter the counter 31 is decremented by the negative-going edge of each reference clock pulse CK.
The output S.sub.6 of the OR gate 28 is applied as well to a differentiation circuit 32, the output S.sub.7 of which is provided to a counter 33, clearing its count value D.sub.4 to zero. The counter 33 is to make the period of the pulses A.sub.2 p times longer than the period T. In this example p=2 and upon each counting of two reference clock pulses CK by the counter 33, an inverter 34 yields a signal S.sub.8 of a duration equal to the period T. The signal S.sub.8 is fed to the gate 27, from which is obtained, as the pulse A.sub.2, output of coincidence between the signals G.sub.1 and S.sub.8 and the reference clock pulse CK.
Data corresponding to the low order n.sub.2 bits or kT contained in the set period data output from the period setting means 21 is provided to an n.sub.2 -bit adder 35, wherein it is added to the output of the n.sub.2 -bit flip-flop 23, and the added output is supplied to data terminals D.sub.0 and D.sub.1 of the flip-flop 23. In this example n.sub.2 =2, so the adder 35 is a 2-bit adder. A carry output C.sub.1 of the adder 35 is applied to a gate 36 after being inverted and to a gate 37 without being inverted. In the initial state the flip-flop 23 is reset and its output is "0", so that the carry output C.sub.1 is "0" and the gate 36 remains enabled. A high order bit output d.sub.2 in the 2-bit output of the adder 35 is high-level since in this example two low order bits of the set period data are "1" and "0", respectively. The output of the adder 35 is applied to the flip-flop 23 upon the fall of the output S.sub.5 from the gate 26 and the output of the flip-flop 23 is provided as the fractional period data RD of the period generator 12. The flip-flop 23 and the adder 35 constitute an accumulator 20.
When the down counter 31 has counted the reference clock pulses CK by the number corresponding to the number m which is set to 7 in this example, that is, when the count value D.sub.1 of the counter 31 is decremented to zero, a zero detector 38 yields an output S.sub.1, which is applied to the gate 36, the output S.sub.2 of which is provided via an OR gate 39 to the gate 26, the output S.sub.5 of which is fed to the OR gate 28. In consequence, the gate 29 produces, as the pulse A.sub.1, one reference clock pulse CK 8T apart from the pulse A.sub.1 which occurred at the start of operation. Moreover, the output generation from the OR gate 28 induces an output from the differentiation circuit 32, by which the counter 33 is cleared and the high order n.sub.1 bits of the set period data are preset in the down counter 31. By the negative-going edge of the output S.sub.5 of the gate 26 the output of the adder 35 is input into the flip-flop 23, the outputs d.sub.3 and d.sub.4 of which go to "1" and "0", respectively. The high order bit output d.sub.3 goes high, so that the output bits of the adder 35 both go to "0s", its carry output C.sub.1 becomes high-level and its output d.sub.2 low-level.
In this state similar operations are performed. When the down counter 31 is decremented to zero next, the output S.sub.1 of the detector 38 is fed to the gate 37, the output S.sub.3 of which is placed by the next reference clock pulse CK into a D flip-flop 41, the outputs S.sub.4 of which is, in turn, applied to the gate 26. Consequently, the pulse A.sub.1 is provided from the gate 29 as in the above, but this pulse A.sub.1 is 9T apart from the preceding pulse A.sub.1. Furthermore, the output S.sub.5 of the gate 26 is applied to the flip-flop 23 to make its output d.sub.3 low-level, with the result that the output d.sub.2 of the adder 35 goes high, thus returning the period generator 12 to the initial state. Therefore, the same operations as described above are repeated. Namely, the period of the pulses A.sub.1 becomes 8T and 9T alternately, the period of the pulses A.sub.2 becomes 2T and the fractional period data RD assumes d.sub.3 =0, d.sub.4 =0 (0T) and d.sub.3 =1, d.sub.4 =0 (0.5T) for the periods of 8T and 9T, respectively. In other words, data corresponding to kT in the output data of the period setting means 21 is accumulated in an accumulation circuit 20 upon each occurrence of the pulse A.sub.1, and the bits d.sub.3 and d.sub.4 in the accumulated output, except the carry bit, are provided as the fractional period data RD. Moreover, the output of the detector 38 is switched by the gates 36 and 37 to the OR gate 39 or the flip-flop 41 acting as a delay, from which it is applied to the gate 26 without being delayed or after being delayed by T.
The fine delay circuit 14 in FIG. 1 has an arrangement such, for instance, as depicted in FIG. 5. The pulses A.sub.1 and A.sub.2 from the period generator 12 are respectively delayed by delay circuits 42 and 43 and supplied as pulses A.sub.1 ' and A.sub.2 ' to gates 44, 45 and 46, 47, respectively, as shown in FIG. 6. The delay circuits 42 and 43 have the same delay time. This delay is effected so that the fractional period data RD is changed prior to the occurrence of the pulse A.sub.1 ', that is, the pulse A.sub.1 is delayed to assure that the added output of the adder 35 has been settled in the flip-flop 23 and its new output has been established at the occurrence of the pulse A.sub.1 '. While the period of the pulses A.sub.1 is 8T, the fractional period data RD is d.sub.3 =0 and by the bit d.sub.3 the gates 44 and 46 are enabled and the gates 45 and 47 disabled. The outputs of the gates 44 and 46 are supplied via OR gates 48 and 49 to gates 51, 52 and 53, 54, respectively, and the outputs of the gates 51 and 53 are provided to OR gates 55 and 56, respectively. In the above example the data d.sub.4 is always "0" and by this bit d.sub.4 the gates 51 and 53 are always enabled and the gates 52 and 54 disabled. Accordingly, while d.sub.3 =0, the pulses A.sub.1 ' and A.sub.2 ' are respectively output as pulses B.sub.1 and B.sub.2 via the gates 44, 48, 51, 55 and 46, 49, 53, 56. While the period of the pulses A.sub.1 is 9T, since d.sub.3 =1 and d.sub.4 =0, the gates 44 and 46 are closed and the gates 45 and 47 open. The pulses A.sub.1 ' and A.sub.2 ' are supplied via the gates 45 and 47 to T/2-delay elements 57 and 58, wherein they are delayed by T/2, and the delayed outputs are provided as the pulses B.sub.1 and B.sub.2 via the gates 48, 51, 55 and via the gates 49, 53 and 56. The occurrence of pulse B.sub.1 produced at this time is 8.5T after the preceding pulse B.sub.1 having passed through the gates 44, 48, 51 and 55. The next pulse A.sub.1 ' passes through the gate 44. Thereafter the same operation repeats itself, making the period of the pulses B.sub.1 8.5T. Incidentally, the outputs of the gates 52 and 54 are provided to the OR gates 55 and 56 via T/4 delay circuits 61 and 62.
FIG. 7 illustrates an example of the coarse delay circuit 16 used in FIG. 1. A clock-synchronous-type counter 63 is cleared by the pulses B.sub.1 and the pulses B.sub.2 are delayed by a delay circuit 64 and are counted, as pulses B.sub.2 ', by the counter 63, as shown in FIG. 8. That is, the counter 63 starts to count the pulses B.sub.2 ' after being cleared. The high order data CDH of the data indicating the set delay time, which is available from the delay setting means 17, is composed of four bits b.sub.1, b.sub.2, b.sub.3 and b.sub.4 representing delay time 16T, 8T, 4T and 2T, respectively, and since only the bit b.sub.3 is "1" and the other bits are "0s", the set delay time is 4T. The high order data CDH and the count value D.sub.5 of the counter 63 are compared by a coincidence detector 65. As depicted in FIG. 8, when the count value D.sub.5 has reached 2, the coincidence detector 65 yields an output S.sub.9, by which a gate 66 is enabled, and the pulse B.sub.2 ' occurring in this while is output as the delayed pulse E.
The fine delay circuit 18 in FIG. 1 has an arrangement such, for example, as shown in FIG. 9. Fractional delay data CDL which is represented by low order bits in the delay data corresponding to the delay time set in the delay setting means 17 is composed of three bits b.sub.5, b.sub.6 and b.sub.7, representing delay time T, T/2 and T/4, respectively, by which pairs of gates 67 and 68, 71 and 72, 73 and 74 are each controlled to be enabled and disabled. The delayed pulse E is applied to the gates 67 and 68. The outputs of the gates 67, 71 and 73 are provided to OR gates 75, 76 and 77, whereas the outputs of the gates 68, 72 and 74 are fed via T, T/2 and T/4 delay elements 78, 79 and 81 to the OR gates 75, 76 and 77. The output of the OR gate 75 is applied to the gates 71 and 72 and the output of the OR gate 76 to the gates 73 and 74. In the case where the fractional delay data CDL is a T/2 delay, the bits b.sub.5, b.sub.6 and b.sub.7 are a "0", a "1" and a "0", respectively, and the gates 67, 72 and 73 are enabled and the gates 68, 71 and 74 disabled. The pulse E passes through the gates 67, 75 and 72, a T/2 delay element 79 and the gates 76, 73 and 77 and is output as the pulse F delayed by 0.5T, as shown in FIG. 8. In FIG. 8 broken-lined ones of the pulses E and F indicate the positions of pulses which occur when the set delay time is zero.
As described above, according to the prior art timing generating device, the operation starts with the creation of the pulse B.sub.1 of a period set in the period generating section 11 and then the pulse B.sub.1 is delayed by a value set in the delay generating section 15. To perform this, the period generating section 11 employs the fine delay circuit 14 and the delay generating section 15 also uses the fine delay circuit 18. In order to produce timing pulses of various periods and phases in small units, that is, to enhance resolution, it is necessary to increase the number of delay switching stages in each of the fine delay circuits 14 and 18 and to use delay elements of small delay amounts. Since the unit of delay by the coarse delay circuit 16 is an integral multiple of the reference clock period T, i.e. 2T in the above example, the number of delay switching stages in the fine delay circuit 18 is greater than in the fine delay circuit 14. For instance, a frequency as high as 250 or 500 MHz has come into use as the reference clock in IC test equipment. In such a case, an extremely high resolution is required and delay elements of high accuracy and stability are needed. Conventional delay elements are mere printed circuits, LC transmission lines, CR transmission lines, gate circuits and so forth. It is difficult, however, to accurately maintain the delay time of each delay element untouched by aging and environmental variations such as a temperature change. In addition, delay elements which are insusceptible to such variations and high in precision are expensive, and the prior art requires such costly delay elements for the both fine delay circuits 14 and 18.